1. Field of the Invention
The present invention relates to a method of fabricating complementary metal-oxide-semiconductor (CMOS) transistor, and more particularly to a method of fabricating CMOS transistor using Si--B layer to form a source/drain extension junction.
2. Description of the Prior Art
Recently, ultra large-scale integration (ULSI) semiconductor technologies have dramatically increased the integrated circuit density on the chips formed on the semiconductor substrate. This increase in circuit density has resulted from downsizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high-resolution photolithography, directional (anisotropic) plasma etching, and other semiconductor technology innovations. However, future requirements for even greater circuit density are putting additional demand on the semiconductor processing technologies and on device electrical requirements.
The fabrication of a metal-oxide-semiconductor field effect transistor (MOSFET) device is well-known. Generally, MOSFETs are manufactured by placing an undoped polysilicon material over a relatively thin gate oxide. The polysilicon material and gate oxide is then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device.
The gate conductor and adjacent source/drain regions are formed using well-known photolithography techniques. Gate conductors and source/drain regions arise in openings formed through a thick layer of what is commonly referred to as field oxide (FOX). Those openings and the transistors formed therein are termed active regions. The active regions are therefore regions between field oxide regions. Metal interconnect is routed over the field oxide to couple with the polysilicon gate conductor as well as with source/drain regions to complete the formation of an overall circuit structure.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on unitary monolithic substrate. While both types of devices can be formed, the devices are distinguishable based on the source/drain impurity dopant. The method by which n-type dopant is used to form an n-channel device and p-type dopant is used to form a p-channel device entail unique problems associated with each device. As layer densities increase, the problems are exacerbated. Device failure can occur unless adjustments are made to processing parameters and processing steps. The n-channel processing must, in most instances, be dissimilar from p-channel processing due to the unique problems of each type of device. The problems inherent in n-channel fabrication will be discussed first followed by p-channel.
The n-channel devices are particularly sensitive to so-called short channel effects. The distance between source and drain regions is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the source and drain, distance between the source and drain regions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel becomes small, the short channel effect becomes a predominant problem.
Generally, the short channel effect impacts device operation by reducing device threshold voltages and increasing sub-threshold currents. As the effective channel length becomes quite small, the depletion regions associated with the source and drain areas may extend toward one another and substantially occupy the channel area. Hence, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short effective channel length. Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold amount, current between the source and drain nonetheless exist for transistors having a relatively short effective channel length.
However, two of the primary causes of increased sub-threshold current are punch-through and drain-induced barrier lowering. Punch-through results from the widening of the drain depletion region when a reverse-bias voltage is applied across the drain-well diode. The electric field of the drain may eventually penetrate to the source area, thereby reducing the potential energy barrier of the source-to-body junction. Punch-through current is therefore associated within the substrate bulk material, well below the substrate surface. Contrary to punch-through current, drain-induced barrier lowering for induced current occurs mostly at the substrate surface. Application of a drain voltage can cause the surface potential to be lowered, resulting in a lowered potential energy barrier at the surface and causing the sub-threshold current in the channel near the silicon-silicon dioxide interface to be increased. One method in which to control short channel effect is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the ensuing device.
Increasing the potential gradients produces an additional effect known as hot carrier effect. The hot carrier effect is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field, occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel.
Using the n-channel example, the electric field at the drain causes channel electrons to gain kinetic energy. Electron-electron scattering randomizes the kinetic energy and the electrons become "hot". Some of these hot electrons have enough energy to create electron-hole pairs through impact ionization of the silicon atoms. Electrons generated by impact ionization join the flow of channel electrons, while the hole flows into the bulk to produce a substrate current in the device. The substrate current is the first indication of the creation of hot carriers in a device. For p-channel devices, the fundamentals of the process are essentially the same except that the role of holes and electrons are reversed.
The hot carrier effect occurs when some of the hot carriers are injected into the gate oxide near the drain junction, where they induce damage and become trapped. Traps within the gate oxide generally become electron traps, even if they are initially filled with holes. As a result, there is a negative charge density in the gate oxide. The trapped charge accumulates with time, resulting in positive threshold shifts in both n-channel and p-channel devices. It is known that since hot electrons are more mobile than hot holes, the hot carrier effect causes a greater threshold skew in n-channel devices than p-channel devices. Nonetheless, a p-channel device will undergo negative threshold skew.
Unless modifications are made to the transistor structure, the problems of sub-threshold current and threshold shift resulting from short channel effect and hot carrier effect will remain. To overcome these problems, alternative drain structures such as double diffused drains (DDDs) and lightly doped drains (LDDs) must be used. The purpose of both types of structures is the same: to absorb some of the potential into the drain and thus reduce the maximum electric field. The popularity of double diffused drain structures has given way to lightly doped drain structures since double diffused drains cause unacceptably deep junctions and deleterious junction capacitance.
A conventional lightly doped drain structure is one whereby a light concentration of dopant is self-aligned to the gate electrode followed by a heavier dopant self-aligned to the gate electrode on which two sidewall spacers have been formed. The purpose of the first implant dose is to produce a lightly doped section of both the source and drain areas at the gate edge near the channel. The second implant dose is spaced from the channel a distance dictated by the thickness of the sidewall spacer. Resulting from the first and second implants, a dopant gradient occurs at the junction between the source and channel as well as the junction between the drain and channel.
A properly defined lightly doped drain structure must be one which minimizes hot carrier effect but not at the expense of excessive source/drain resistance. The addition of a lightly doped drain implant adjacent the channel unfortunately adds resistance to the source/drain path. This added resistance, generally known as parasitic resistance, can have many deleterious effects. First, parasitic resistance can decrease the saturation current (i.e., current above threshold). Second, parasitic resistance can decrease the overall speed of the transistor.
A properly designed lightly doped source/drain, which overcomes the above problems, must therefore be applicable to both an n-channel transistor and a p-channel transistor. However, the approach will be used in CMOS processes. The CMOS transistor is readily fabricated within existing process technologies. In accordance with many modem fabrication techniques, it would be desirable that the improved CMOS transistor be formed having low resistance and the ultra shallow junction.